It has always been a challenge to introduce timing verification early into the industrial development process as the inputs required for the verification, in particular the worst-case execution time and the system behaviour description, are moving targets all across the different development process phases. Thanks to the introduction of model based methods (and the ability to express non-functional properties with dedicated, concern-specific viewpoints) in the industrial development process, this goal seems to be in the reach. Starting from very high level system architecture and rough timing allocations, the timing verification has to be refined at each step of the project (architectural design, detailed design, coding, unit test and software validation phases) down to concrete timing measurements on the final delivered system. A major problem however persists: model-based timing verification techniques, such as scheduling analysis and simulation, are often not directly applicable to conceptual design due to the semantic gaps between their respective models. Solving this issue is essential to break the remaining walls separating model-based timing verification from the development process of real-time embedded systems, and to enable its use in the industry.
PolarSys Time4Sys provides meta-models, transformation rules, and authoring tools required to perform analysis or simulation of the timing aspects in the design of a real-time system to verify the consistency and performance of a given scheduling model. PolarSys Time4Sys doesn’t provide any timing analysis or simulation tools of its own but rather provides gateways to existing tools (both commercial and open-source).
It represents a contribution to the industrial exploitation of model-driven technologies and timing verification techniques in the design of real-time systems in a variety of application domains.
PolarSys Time4Sys provides a framework that fills the gap between the capture of timing aspects in the design phase of a real-time system and the ability of specific/dedicated tools to verify the consistency and performances of a given scheduling.
Time4Sys is composed of two building blocks (the Design and the Analysis pivot models) as well as a set of transformation rules between them.
Design Pivot Model
Time4Sys Design model uses a subset of the MARTE OMG standard as a basis to represent a synthetic view of the system design model that captures all elements, data and properties impacting the system timing behaviour and required to perform scheduling analysis or simulation (e.g. tasks mapping on processors, communication links, execution times, scheduling parameters, etc.). Time4Sys Design is not limited to the use of a particular design modelling tool and environment. It can be connected to various environments and languages such as UML, SysML, AADL, or any other proprietary environment (e.g. Capella).
Scheduling analysis and simulation are seldom directly applicable to the conceptual design models in general and to Time4Sys Design models in particular due to the semantic mismatch between the latter and the variety of analysis and simulation models known from the classical real time systems research and represented by academic and commercial tools.
Analysis Pivot Model
Time4Sys Analysis pivot model is based on generic modelling concepts known from the classical real time systems research, such as tasks, processors, busses, scheduling parameters (priorities, time slots, deadlines, etc.). Time4Sys Analysis models preserve the timing behaviour modelled in the corresponding Time4Sys Design models, while ensuring the compatibility with the variety of existing timing verification tools. Same as Time4Sys Design, Time4Sys Analysis is not limited to a specific timing verification tool. This ensures a minimum of independence from the timing verification tools specificities and allows hiding its complexity to the designer. If required, one timing verification tool can be easily replaced by another. Ultimately, several tools could also be used together to run a timing verification. After timing verification in the selected tool, results are injected in Time4Sys Analysis. Then, they are translated to be compliant with the original design model and reinjected back in Time4Sys Design.
Today, the use of a given timing analysis/simulation tool in a design environment requires specific adaptations, that are often complex and error-prone due to the potential semantic mismatch between the design environment and the tool.
Thanks to Time4Sys, the adaptation of a tool is done once for all and can benefit to any design environment that integrates Time4Sys.
This allows the designers to use several tools to perform cross-checks or identify a domain of solution with a first tool and further refine with another.
We believe that Time4Sys will provide a collaboration workspace between industrial end-users (system designers), tools vendors and academics.
Moreover, considering that Time4Sys is built on top of existing Eclipse projects (EMF, SiRIUS, KitAlpha), and targeting integration with System Design tools already hosted in Polarsys (Papyrus, Capella), it shall find a consistent place in the Polarsys ecosystem.
The initial contribution shall be triggered by the end of 2016 or in the early 2017.
By the end of 2017, the following developments shall be contributed:
- Enriched versions of the editors
- Gateways with open source timing verification tools: MAST, Cheddar
These features shall be contributed by academics before mid 2018
- Support for stochastic analysis
- Support for choosing the right tool (or workflow of tools), regarding the available design inputs and expectations